Various transmission lines, such as a grounded coplanar line in which a ground electrode is disposed substantially all over one surface of a dielectric plate and a coplanar line is disposed on the other surface of the dielectric plate, a grounded slot line in which a ground electrode is disposed on one surface of a dielectric plate and a slot is arranged in the other surface of the dielectric plate, and a planar dielectric transmission line (PDTL) in which slots facing each other across a dielectric plate are arranged in both surfaces of the dielectric plate, are used as transmission lines for a microwave band or a millimeter-wave band.
Each of such transmission lines includes two parallel planar conductors. Thus, for example, if an electromagnetic field is disturbed in an input/output portion or a bend of a line, there is a problem that a wave in a spurious mode, such as a so-called parallel-plate mode, is induced between the two parallel planar conductors (between the parallel planer conductors) and such a wave in the spurious mode (hereinafter, simply referred to as an “undesired wave”) propagates between the planar conductors. The occurrence of such propagation (leakage) of an undesired wave causes a problem in that interference by the undesired wave is generated between adjoining lines and such interference causes leakage of a signal. In addition, since part of energy of a transmission wave is leaked as an undesired wave and is not reconverted into a transmission wave, transmission loss is generated.
In order to prevent such propagation of an undesired wave, a technology for alternately connecting inductor portions and capacitor portions and arranging the inductor portions and the capacitor portions on a two-dimensional plane is disclosed in “Nonleaky Conductor-Backed CPW Using A Novel 2-D PBG Lattice”, 1998 APMC (non-patent document 1). In addition, a technology in which, as shown in FIG. 13A, a plurality of through holes 11 for allowing conduction between parallel planar conductors is arranged in a dielectric substrate forming a waveguide including the two parallel planar conductors and a technology in which, as shown in FIG. 13B, for example, an undesired-wave propagation blocking circuit 12 is disposed at a planar conductor on a front surface side of a dielectric substrate using conductor patterns comprising electrodes for generating capacitances between the electrodes and a planar conductor on a rear surface side and a plurality of lines that is connected to the electrodes and that forms inductors are disclosed in Japanese Unexamined Patent Application Publication No. 2000-101301 (patent document 1). In FIGS. 13A and B, the mark “x” represents a signal propagation direction of a slot line, and wavy lines represent states of propagation of undesired waves.
In addition, as the above-mentioned undesired-wave propagation blocking circuit, as shown in FIGS. 14A and B, a technology for arranging spiral parallel line resonators is disclosed in Japanese Unexamined Patent Application Publication No. 2003-258504 (patent document 2).
FIG. 14B is a partial plan view of a high-frequency circuit device including an undesired-wave propagation blocking circuit, and FIG. 14A is a partial plan view of the undesired-wave propagation blocking circuit. Planar conductors 2 are provided on the upper and lower surfaces of a dielectric substrate 1. Undesired-wave propagation blocking circuits 4 are disposed at the planar conductors 2. As shown in FIG. 14A, each of the undesired-wave propagation blocking circuits 4 includes two parallel transmission lines, transmission lines 7A and 7B, and resonators 8 are connected to the transmission line 7A. Each of the resonators 8 has two spiral lines, spiral lines 8A and 8B, that extend in parallel to each other from a root portion of the resonator 8, and leading ends of the spiral lines 8A and 8B are connected to each other at a point represented by 8C. The arrows E in the figures represent electric field vectors generated between two transmission lines.
The undesired-wave propagation blocking circuit 4 is formed by arranging a plurality of such pairs of transmission lines and resonators, as shown in FIG. 14B.
However, the structure including the through holes needs increased manpower for through-hole processing. Thus, the cost increases. In addition, in the structures in non-patent document 1 and patent document 1, since the undesired-wave propagation blocking circuits are large in size, the wafer size increases, and thus the cost increases. Moreover, the structure in patent document 2 has a problem in that an effective bandwidth in which propagation of an undesired wave is blocked is relatively narrow.